1. Field of the Invention
The invention relates to semiconductor devices containing an interconnection structure comprising conductive wiring and conductive vias on a substrate and, more particularly, to a damascene structure that defines conductive paths and/or vias on a substrate and a method of fabricating same.
2. Description of the Background Art
The escalating requirements of density and performance associated with ultra large scale integrated circuits require responsive changes in interconnection technology. High density integrated circuits require planarized layers of interconnection paths and vias with minimal spacing between conductive paths. U.S. Pat. No. 5,262,354 discloses a three-step damascene technique for forming electrically conductive vias and interconnection lines on a substrate. Additionally, in U.S. Pat. No. 5,635,423, a simplified dual damascene process is disclosed for providing a multi-level metallization and interconnection structure wherein conductive vias and paths are formed simultaneously.
The dual damascene process taught in the ""423 patent involves forming a first insulative layer (e.g., a layer of silicon oxide) upon a substrate and a silicon nitride etch stop layer upon the first insulative layer. A second insulative layer (e.g., silicon oxide) is formed on the etch stop layer and a first opening of about the size of the ultimate via is formed in the second insulative layer. Using a mask, a trench is formed in the second insulative layer while simultaneously forming a via in the etch stop and the first insulative layer. Subsequently, the mask is removed and a conductive material is simultaneously deposited in the via and trench.
Existing dual damascene processes utilize silicon dioxide as the insulator between the substrate and the conductive path, as well as between conductive paths. Also, the conventional dual damascene process uses silicon nitride as an etch stop to prevent distortion of the via size during the final etch step. The final etch step is generally used to create the via, as well as the interconnection trench, prior to filling the via and interconnection with a conductive material. The use of silicon nitride as an etch stop and a conventional photo-resist to define the trench in the second insulative layer can provide for very high selectivity for the etch process.
As integrated circuits have become more dense and switching speeds have increased, the materials used to fabricate the circuits and the conductive interconnections have been scrutinized. To reduce signal delay and cross-talk between conductive interconnections, insulative materials with low dielectric constants (e.g., k less than 3.5), known as xe2x80x9clow k materialsxe2x80x9d, are becoming widely used, e.g., these materials are sold under the tradenames Flare 2.0, PAE-2, FPI, BCB, and the like. However, when organic or carbon-based low k materials (e.g., amorphous fluorinated carbon (a-C:F)) are used as the insulative layer within a single or dual damascene structure, the etch selectivity to conventional photoresist is poor when using an oxygen-based etch chemistry. In such situations, the dual damascene process sequence is conventionally modified to incorporate a xe2x80x9chard maskxe2x80x9d fabricated of silicon dioxide or silicon nitride to define the trench. Such a silicon dioxide hard mask is not etched by the oxygen chemistry. Additionally, silicon nitride or silicon dioxide etch stop is also still used within the dual damascene structure. Consequently, the conventional low k dual damascene structure utilizes a material for the etch stop and hard mask that is distinct from the structure materials. Additionally, the hard mask and etch stop materials must be patterned using conventional photoresist techniques, necessitating numerous processing steps.
There has also been development in the use of plasma polymerized methylsilane (PPMS) material and other radiation sensitive organo-silicon materials as photoresists. The use of PPMS as a photoresist is disclosed in U.S. Pat. No. 5,439,780 issued Aug. 8, 1995 and herein incorporated by reference. Such radiation sensitive materials have not heretofore been used in conjunction with integrated circuit structures that include low k dielectric materials.
Therefore, there is a need in the art for a damascene structure and a method of fabricating such a structure that uses a photosensitive, silicon-based resist material which can function as a good hard-mask or etch-stop for patterning low k materials.
The invention overcomes the disadvantages associated with the prior art by providing a method of fabricating a damascene structure containing an insulative material having a low dielectric constant (e.g., k less than 3.5), hereinafter referred to as a low k material, using a silicon-based, organic material such as plasma polymerized methylsilane (PPMS) as a hard mask, etch stop and photoresist material. Both single and dual damascene structures benefit from such a use of silicon-based, organic material.
The process by which a dual damascene structure is fabricated in accordance with the invention begins by applying a film of low k material onto a semiconductor substrate; a layer of PPMS or other photosensitive silicon-based, resist material is deposited upon the low k film; and the resist is exposed to UV light according to a specific pattern for a via. When PPMS is used, the area of the PPMS layer exposed to the UV light is converted to plasma polymerized methylsilane oxide (PPMSO) and the unexposed area remains PPMS. The imaged layer is then developed by removing the PPMS using a chlorine (Cl2) or Cl2/HBr-based etchant to form a patterned layer of PPMSO. In this step, the underlying low k film is not affected by the etchants. Next, an additional low k film is deposited over the patterned PPMS layer. Thereafter, another layer of PPMS is uniformly deposited onto the second low k film. The second PPMS layer is exposed to UV light according to an interconnect pattern (i.e., the surface of the PPMS is masked), where the exposed area is converted to PPMSO and the unexposed area remains PPMS. The PPMS is etched with chlorine (Cl2) or Cl2/HBr-based etchant to define the interconnect pattern defining a trench.
The etch chemistry is then changed and the exposed layers of low k film are etched using an oxygen-based chemistry. The second layer of PPMSO behaves essentially as would a hard mask as it is not affected by the oxygen chemistry, while the first layer of PPMSO serves as an etch stop. The result of the etch is a dual damascene structure having at least one trench interconnected with a via. The dual damascene structure is then metallized and planarized to simultaneously form a conductive via and interconnection line. Planarization of the metallization is accomplished using, for example, chemical-mechanical polishing. The metallization is then conventionally passivated. Generally, passivation is accomplished using an H2-based chemistry to clean the surface oxide, followed by deposition of a layer of, for example, silicon-nitride, to prevent the copper surface from damage through the next series of steps needed to complete the next layer within the integrated circuit. For example, a cure process for a low k material may require a high temperature (400-450xc2x0 C.) O2-based atmosphere that can severely oxidize the copper and increase the via/trench interface resistance among other detrimental effects. Additionally, low k material etch requires an O2-based chemistry that can also oxidize the exposed copper, if any.
The PPMSO has a very high resistance to oxygen plasma, with etch selectivity greater than 50 compared to the low k films being etched in an oxygen based chemistry. It is this high resistance to oxygen plasma that makes the PPMSO an excellent etch stop for etching low k materials when using an oxygen-based plasma.
To form a single damascene structure, a first layer of low k material is deposited upon a substrate and a layer of PPMS (or another silicon-based resist material) is deposited upon the layer of low k material. The PPMS is then masked and exposed to UV light to form PPMSO at the exposed regions of the mask. A chlorine etch chemistry is used to remove the PPMS and form a patterned layer of PPMSO. The pattern defines locations for vias through the first layer of low k material. An oxygen-based etch chemistry is then used to remove the low k material at the via location. As such, the patterned layer of PPMSO is used as a hard mask during the oxygen-based etch process.
Next, a metallization layer is deposited over the via pattern and the layer is planarized such that only the via is filled with metallization. A copper passivation layer is deposited over the planarized structure. As mentioned above, the passivation is accomplished using an H2-based chemistry to clean the copper and then depositing, for example, a silicon-nitride layer over the copper.
The foregoing steps are repeated to form a trench that connects to the via. Specifically, a second low k material layer is deposited over the passivation layer; a second PPMS/PPMSO layer is deposited, patterned and etched; an oxygen-based etchant is used to etch the low k material to form a trench; a fluorine-based chemistry is then used to remove the passivation layer; the trench is metallized and planarized; and the planarized trench metal is passivated as previously described. The result is a single damascene structure that is formed using a silicon-based, photoresist material (e.g., PPMS) as a hard mask during the oxygen-based chemistry etching steps.
Another important feature of the present invention is that a dual damascene structure can be fabricated using a single lithography step and single development and pattern transfer etch sequence. This application of the invention takes advantage of the combination of unique features of a PPMS resist. Specifically, the invention utilizes the ability to control the degree of photo-oxidation with UV exposure, which in turn determines the amount of PPMS or PPMSO (depending on development process tone) that remains on the device. This allows the formation of a bilevel hard mask structure using a single lithography step employing a two-tone (grey-scale) mask, or a sequence of exposures using two standard masks. This approach is aimed specifically at the patterning of dual damascene structures in low k organic polymer or amorphous carbon based films, which may be etched with high selectivity through a PPMS/PPMSO masking layer using an oxygen based plasma.
When using a negative tone process, the combination of trench and contact vias are patterned in a single step using a grey level mask (i.e., one having clear, partially absorbing (grey) areas, and totally absorbing areas) or a sequence of two ordinary masks so as to create a pattern in which some areas are totally exposed, some areas partially exposed, and some areas unexposed. For negative tone applications those areas of the dielectric stack intended to remain after etching are completely exposed, those areas to be removed in the upper layer of low k dielectric (the trench) are partially exposed, and those areas to be removed in both layers (i.e., the contact vias) remain unexposed.
The PPMS development, trench, and via etch may then conducted in a single etch sequence. PPMS development is performed using a Cl2 or Cl2/HBr based plasma etch for a time sufficient to remove all of the completely unexposed PPMS and part of the partially exposed PPMS. The amount of PPMS left behind in the partially exposed area will depend on the relative amount of light (i.e., the percent transmission of the grey tone mask area) and the total etch time (including overetch time) necessary to clear the unexposed regions of PPMS. The thickness of material remaining in the partially exposed area is thereby controlled by choice of initial film thickness, exposure level, and overetch time such that the remaining material may be removed in the same etch time necessary to subsequently remove a thin inorganic (oxide or nitride layer) etch stop layer between the two layers of organic dielectric material.
Next, the etch gases are switched to an oxygen based mixture (including pure oxygen, or oxygen with N2, CO2, CO, SO2, or other additives) so as to selectively and anisotropically etch through the top layer of the organic low k dielectric and stop on the thin inorganic etch stop layer. Under these etch conditions, the surface of the PPMS/PPMSO top layer converts to a hard oxide etch mask, thereby protecting underlying material from etching. Thereafter, the etch gases are switched to generate a fluorine based plasma. Typical etch gases include fluorocarbons, hydrofluorocarbons, SF6, NF3, their mixtures, or any other plasma etch chemistry known to selectively etch oxide over the underlying low k organic material. The duration of this etch must be sufficient to remove both the partially exposed (i.e., thin regions) of PPMS/PPMSO imaging layer and the thin inorganic etch stop layer, but not to remove all of the completely exposed PPMS/PPMSO layer. The etch gases are switched back to give an oxygen based plasma. In this step, the lower layer of low k dielectric material is anisotropically etched down to the underlying substrate forming the contact via, while the now uncovered top layer is etched to form the trench (to be filled with metal to form the interconnect wire). Finally, it may be desirable (but not necessarily required) to perform a final etch step using a fluorine based plasma to remove the remaining top layer of PPMS/PPMSO and the exposed area of the inorganic etch stop layer. This etch sequence, which may be performed in a single chamber or in separate chambers, completes the fabrication of a low k dual damascene structure which may then be filled with metal to form an interconnect structure.
The same structure may also be formed using a positive tone development process. The first step of this process employs a mask structure essentially opposite to that of the negative tone process described above. Again either a single grey level mask (i.e., one having clear, partially absorbing (grey) areas, and totally absorbing (black areas) or a sequence of two ordinary masks is used to create a pattern in which some areas are totally exposed, some areas partially exposed, and some areas unexposed. For positive tone development, the areas in which the entire dielectric stack is to remain are unexposed, those areas to be removed in the upper layer of low k dielectric are partially exposed (this is the same as for the negative tone), and those areas to be removed in both layers are totally exposed.
Development of positive tone patterns is performed using either a wet etch process employing buffered oxide etch solutions or using HF vapor. Development time is controlled so as to remove all or essentially all of the PPMS/PPMSO in the totally exposed region, and some (the upper regions) of PPMS/PPMSO in the partially exposed regions, while leaving unexposed material essentially the same. The resulting bilevel pattern may then be transferred through the underlying layers using the same steps as described for the negative tone process.
It may also prove advantageous, for some applications, to add an additional step to the positive tone sequence in which the patterned PPMS mask is blanket exposed to UV light so as to uniformly oxidize it throughout its thickness. This is particularly the case if using positive tone development conditions in which some residue remains in the totally exposed regions. In such a case, it is necessary to add an additional step at the beginning of the dry etch sequence in which a fluorine based plasma etch is applied long enough to clear any residue remaining on the surface of the totally exposed regions. Even a thin layer of residue, if allowed to remain, may act as a mask to prevent etching of the underlying organic low k material.